The preent invention relates generally to field effect transistors (FETs) and to the preparation of integrated circuits containing a plurality of the FETs. More particularly, the present invention is related to a novel FET having a field insulator which is nonrecessed with respect to the source and drain regions, and having a polycrystalline silicon gate which is self-aligned with respect to both conductive and nonconductive regions, and to a method for fabricating such FETs and integrated circuits containing a plurality of such FETs. The present invention requires only four basic lithographic (pattern delineating) masking steps to achieve the desired integrated circuit containing an array of FETs and the associated addressing, decoding, sensing, and/or clocking circuits which are positioned peripherally to the array.
The FET is an important electrical switching device in large scale integrated circuits. Such circuits may contain tens or even hundreds of thousands of FETs on a single semiconductor chip. Such chips typically measure less than one quarter of one inch on a side. The physical size (i.e., the lateral dimensions) of the FET switching device and the ease of electrically interconnecting a plurality of FETs are important factors in determining how closely devices may be packed into a given chip area. Thus, the degree of integration is in part determined by the device packing density. Accordingly, continuing work is being carried out to provide new masking and etching procedures which will yield the minimally smallest structure for a given lithographic feature size without significantly increasing the complexity of the fabrication process.
The choice of the conductive gate material for the FET influences the properties of the FET and the procedure for fabricating the FET. The most common gate materials are aluminum (a low-melting temperature metal) and polysilicon (a high-melting temperature nonmetal). Gate materials less commonly used in the industry are high-melting temperature metals such as tungsten and molybdenum which, nevertheless, tend to become unstable from exposure to high processing temperatures. The present invention relates generally to FETs wherein the gate is of polysilicon.
In the fabrication of FETs, it is desirable to use polysilicon for the gate of the FET. As is well known in the art, polysilicon is an attractive FET gate material because of its ability to withstand high processing temperatures without degradation. Furthermore, polysilicon offers potentially higher gate oxide reliability than other gate materials. In addition, polysilicon can serve as an interconnection material. Moreover, conductive or semiconductive polysilicon can be converted to nonconductive (insulating) silicon dioxide by high temperature exposure to, for instance, oxygen or water vapor. Furthermore, polysilicon can be coated with an insulating layer such as a silicon dioxide or silicon nitride layer by chemical vapor deposition at high temperature. In addition, it is relatively easy to fabricate source and drain regions self-aligned with respect to the edges of a polysilicon gate. In the self-aligned gate technique, the polysilicon gate is delineated prior to forming the source and drain regions. The edges of the gate material and the edges of the field isolation regions serve as a mask for defining the boundaries of the diffused or ion implanted source and drain regions. A method of fabrication for ion implanted self-aligned source and drain regions is described in "Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions" by R. H. Dennard et al, IEEE J. Solid-State Circuits, Vol. SC-9, pp. 256-268 (October 1974).
In known polysilicon gate FETs, the sides of the channel region are defined by the thick insulation region, commonly referred to as the field isolation region, and the polysilicon gate extends up onto (i.e., overlaps onto) the field isolation regions. The field isolation is typically of silicon dioxide and can exist above, or may be partially or fully recessed into the semiconductive substrate with respect to the source and drain regions.
In FET structures known in the art, the sides of the channel are determined by the field isolation oxide and the polysilicon gate overlaps onto this field oxide. This overlap is necessary because the field isolation lithographic pattern and the polysilicon gate lithographic pattern cannot be automatically registered with respect to one another. Consequently, a misregistration tolerance (i.e., a pattern overlap) must be provided to insure that the source and drain do not electrically short together. This required gate overlap undesirably consumes extra area. Furthermore, at the edges of the polysilicon, a topological step occurs which can lead to coverage problems for subsequently fabricated insulation layers and metallic interconnection lines. An example of the polysilicon overlap and the resultant step in the cross section is illustrated in FIG. 1 of "Uses of Ion Implantation in Advanced MOS Field-Effect Transistors", ECS Fall Meeting Extended Abstracts, Volume 75-2, pp. 326-329, October 1975 by Dennard et al.
Therefore, an object of the present invention is to provide FETs wherein the polysilicon gate does not overlap onto the field isolation. A further object of the present invention is to provide FETs wherein the field isolation is nonrecessed with respect to the FET source and drain regions.
It is also an object of the present invention to provide FETs of reduced overall area without increasing the number of basic lithographic masks used to obtain such. Still another object of the present invention is to provide FETs with a polysilicon gate that is self-aligned with respect to both the conductive source and drain regions on its ends, and to the nonconductive field isolation on its sides. This double self-alignment feature results in a polysilicon gate, the lateral dimensions and location of which correlate directly with the lateral dimensions and location of the channel region of the FET and, therefore, the polysilicon gate material neither overlaps nor underlaps the field isolation regions.
FET integrated circuits are fabricated using a sequence of lithographic masking, exposing, and etching steps. In order to delineate the field isolation; gates of the FET; contact holes to gates, sources, and drains; and metallic interconnection pattern, a minimum of four basic lithographic pattern delineations are generally required. The lithographic masking steps involved in preparing integrated circuits are among the most critical. The lithographic masking steps require high precision in registration (i.e., in relative mask-to-mask alignment) and extreme care in execution. If the misregistration from mask-to-mask is too large, electrical shorts or opens in the integrated circuit will appear and the circuit will not function correctly. Consequently, a misregistration tolerance must be provided to allow for mask-to-mask alignment difficulties. All lithographic exposure systems have a finite misregistration due to the inherent physical limitations that naturally occur in an electromechanical system. Furthermore, each additional lithographic masking step in a process introduces possible surface damage due to mask defects, and increases mask-to-mask registration problems that decrease the processing yield and, accordingly, significantly increase the fabrication cost. A basic objective in FET integrated circuit fabrication is to provide a mask sequencing and associated geometrical layout technique that will result in structure which are more tolerant of mask-to-mask misregistration and yet which provide FET structures of small overall size, without increasing the number of lithographic masking steps.
Accordingly, an object of the present invention is to provide a technique which is more tolerant of mask-to-mask misregistration and which also provides relatively small area FETs. Another object of the present invention is to provide a fabrication process for producing FET integrated circuit arrays which requires a minimum number of lithographic masking (pattern delineating) steps.
In the polysilicon gate FET technology, the polysilicon regions must be electrically connected to highly conductive metallic interconnection lines. In the present invention, this connection can be made by growing and/or depositing an insulating layer over the gate, and then delineating and etching a contact hole or via through the insulating layer. However, such a method of providing electrical connection between the polysilicon gate and the metallic interconnection line suffers from the problem that the polysilicon lithographic pattern and the via lithographic pattern cannot be perfectly registered with respect to one another. Similarly, the via lithographic pattern and the metallic interconnection line lithographic pattern also cannot be perfectly registered with respect to one another.
A fabrication sequence which eliminates this particular problem of contact alignment between the polysilicon gate and the metallic interconnection line and which is preferably employed in the present invention is discussed by Kalter et al. in IBM Technical Disclosure Bulletin, Volume 14, No. 10, p. 3176, March 1972, and by Rideout in IBM Technical Disclosure Bulletin, Volume 17, No. 9, p. 2802, February 1975. Both IBM Technical Disclosure Bulletin publications describe polysilicon gates that overlap onto the field isolation regions. The fabrication process suggested by Kalter et al provides a polysilicon gate FET in which a metal line is "self-registered" with respect to a polysilicon gate, wherein oxidation over the polysilicon gate is prevented by an oxidation barrier gate-masking layer. When the oxidation barrier layer is removed, the entire gate area is revealed for contacting. A metal word line such as aluminum that crosses the polysilicon gate will provide an electrical connection to that gate. Because the entire gate area is revealed, the metal word line and the polysilicon gate advantageously do not need to be precisely registered with respect to each other in order to make electrical connection. Much more precise registration is required, however, when the metal line must contact the polysilicon gate via a conventional contact hole etched through an oxide layer that exists over the gate.
Still another object of the present invention is to provide FETs with improved resistance to electrical leakage as well as having a highly planar surface topology upon which to delineate the metallic-type interconnection pattern. These are accomplished by providing field isolation which is nonrecessed with respect to FET source and drain regions, and by eliminating overlap of the polysilicon gate material onto the field isolation together with providing the upper surface of the field isolation at the same level as the upper surface of the polysilicon gate when desired.
The isolation thickness according to the present invention can be approximately the same over the source and drain regions as it is over the field regions thereby giving desirable low capacitance between source and drain regions and metallic type interconnection lines which cross thereover. In the present invention, the nonrecessed field isolation is approximately planar surrounding the source and drain junctions and thereby beneficial reduction of leakage in the junctions is realized.
A still further object of the present invention is to provide a plurality of FETs of very high packing density interconnected to form an integrated circuit wherein the FETs have been formed on the same semiconductive substrate.
In addition, it is an object of the present invention to provide FET integrated circuit arrays having all of the following desirable aspects:
(1) thick field isolation located between FETs of the array;
(2) field isolation nonrecessed with respect to upper surface of the source and drain regions of the FET;
(3) doped polysilicon gate self-aligned with respect to the field isolation region;
(4) doped source and drain self-aligned with respect to the polysilicon gate; PA1 (5) a metallic-type high electrical conductivity interconnection line; PA1 (6) electrical connection between the doped polysilicon gate and the metallic-type high electrical conductivity interconnection lines; PA1 (7) contact holes or vias for connecting source and drain regions to interconnection lines; and PA1 (8) electrical connection to semiconductive substrate.
A further object of the present invention is to provide a fabrication process which requires a minimum number of basic lithographic masking steps in order to prepare integrated circuit arrays containing FETs having all of the above-described desirable characteristics.